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stratum 3+ simplified control timing modules stm-s3+ 2111 comprehensive drive aurora, illinois 60505 phone: 630- 851- 4722 fax: 630- 851- 5040 www.conwin.com application the connor-winfield stratum 3+ simplified control timing module can be used as a complete system clock module for any stratum 3 timing application in which the design requires the added capabilities of a stratum 3e level hold over within 5c variation in accordance with gr-1244-core-1995. connor-winfield?s stratum 3+ timing module helps reduce the cost of your design by minimizing your development time and maximizing your control of the system clock with our simplified design. features ? 4 operational modes stratum 3 clocking system stratum 3e hold over accuracy 5 hitless reference switching 5 active alarms guaranteed free run lock time of 100 secs tvl alarm us headquarters: 630-851-4722 european headquarters: +353-62-472221
preliminary data sheet #: tm021 p age 2 of 12 rev: p03 date: 06/27/01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice general description the connor-winfield stratum 3+ simplified control timing module (stm-3+) meets every stratum 3 requirement of gr-1244-core-1995. in addition, it also provides the enhanced hold over accuracy of statum 3e specifications over 5 c range. control loop filters effectively attenuate any reference jitter and smooth out phase transients. the stm-3+ is designed to be controlled externally. full external control input allows the user to select and monitor any of the four possible operating modes: free run mode (a=0, b=0 =>free run=1) normal mode #1 (a=1, b=0 => ref 1=1) normal mode #2 (a=0, b=1 =>ref 2=1) hold over mode (a=1, b=1 =>hold over=1) table 4 illustrates the control signal inputs (a,b) and the corresponding operational modes. real-time indication of the operational mode is indicated by unique operating mode outputs on pins 1-4. in addition, all outputs can be placed into a high impedence state when a high signal is placed on the tri-state control pin normal mode #1 results in an output signal that is phase locked to the external reference input #1. normal mode #2 results in an output signal that is phase locked to external reference input #2. hold over mode results in an output signal at or near the frequency as determined by a past historical value and the holdover performance of the stm. the historical value is updated every 40 secs. in the absence of external control inputs, the stm enters the default free run mode and signals an external alarm. free run mode is a guaranteed 4.6 ppm of the nominal frequency. the stm-s3+ provides an alarm pin that goes high during an alarm condition. alarm signals are generated at the alarm out pin during the following conditions: holdover free run loss of lock (lol) loss of reference (lor) tune-limit (pll_tvl) a tune-limit (pll_tvl) alarm signal indicates that the voltage controlled ocxo tuning voltage is approaching within the 10% limit of its lock capability and lol may soon occur. functional block diagram figure 1 package layout figure 2 ?a-a? detail ?a-a? .082 (2.08mm) .040 (1.02mm) .120 (3.05mm) .030 (.762mm) .150 (3.810mm) 2.40 + 0.02 (60.96mm) 2.000 (50.80mm) .192 (4.876mm) 3.95 + 0.02 (100.330mm) .300 typ (22) (7.62mm) .445 (11.30mm) pin 1 .200 (5.08mm) .650 + 0.02 (16.50mm) 24 1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 10 13 12 14 11 bottom view

stm-s3+ cntl a cntl b 0 1 2 3 hold over ref 1 ref 2 free run ex ref 1 2 :1 mux stratum 3+ ocxo dac filters phase comparator clock_out sync_out pll tvl alarm out tuning limit monitor dac fifo pll tvl free run hold over lock detect ex ref 2 stratum 3 tcxo
preliminary data sheet #: tm021 p age 3 of 12 rev: p03 date: 06/27/01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice absolute maximum rating table 1 stm-s3+ symbol parameter minimum nominal maximum units notes v cc power supply voltage (vcc to gnd) -0.5 - +7.0 volts 1.0 v in input voltage -0.5 - +5.5 volts 1.0 t stg storage temperature -40.0 - +90 deg. c 1.0 operating specifications table 3 stm-s3+ parameter specifications notes frequency range 16.384 mhz, 19.44 mhz, 38.88 mhz supply current 350 ma typical, 550 ma during warmup timing reference inputs gr-1244-core 3.2.1, r3-1 jitter, phase transient and wander tolerances gr-1244-core 4.2-4.4 wander genration gr-1244-core 4.2-4.4 free run accuracy 4.6 ppm holdover stability (0 - 70) 0.039 ppm (5c) 0.012 ppm 4.0 initial offset 0.001 ppm 0.001 ppm temperature 0.035 ppm 0.010 ppm drift 0.003 ppm 0.001 ppm holdover history 40 sec pull-in / hold-in range 4.6 ppm 5.0 lock time < 100 sec lock accuracy 0.001 ppm 6.0 pll-tvl alarm limits within 10% of tuning range limit, see fig 8 recommended operating conditions table 2 stm-s3+ symbol parameter minimum nominal maximum units notes v cc power supply voltage (vcc to gnd) 4.75 5.0 5.25 v v por power-on reset voltage level 4.25 4.5 v 2.0 v ih high level input voltage (ttl compatible) 2.0 5.25 v v il low level input voltage (ttl compatible) 0.0 0.8 v t in input signal transition time 250.0 ns c in input capacitance 15.0 pf v oh high level output voltage @ioh=8.0 ma, vcc minimum 2.4 v 3.0 v ol low level output voltage @ioh=8.0 ma, vcc maximum 0.4 v t hl clock out transition time high-to-low, no load 4.0 ns t lh clock out transition time low-to-high, no load 4.0 ns t rip input 8 khz reference signal positive pulse width 30.0 ns t rin input 8 khz reference signal negative pulse width 30.0 ns t ab mode select response 2 ms t op standard opearting temperature 0.0 70.0 deg. c
preliminary data sheet #: tm021 p age 4 of 12 rev: p03 date: 06/27/01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice bottom view +5vdc ex ref 1 gnd ex ref 2 gnd n/c clock_out gnd n/c sync_out gnd pll tvl hold over ref 1 ref 2 free run gnd n/c n/c tri-state n/c alarm out cntl a cntl b pin assignment figure 3 typical application figure 4
operational modes table 4 control input pins operational mode output indicator pins tri-state a b ref 1 ref 2 hold over free run pll_tvl alarm out *clock-out sync out 0 0 0 free run (default) 0 0 0 1 0 2 per spec normal 1 0 0 0 0 0 per spec 0 1 0 mode #1 tune limit 1 0 0 0 1 1 per spec lor + lol 1 0 0 0 0 1 per spec normal 0 1 0 0 0 0 per spec 0 0 1 mode #2 tune limit 0 1 0 0 1 1 per spec lor + lol 0 1 0 0 0 1 per spec 0 1 1 hold over mode 0 0 1 0 0 or 1 1 per spec 1 x x tri-state mode high impedence operational mode 5 volt dc power supply network timing reference input e g . bits independent clock system clock system control and data inputs loss of reference monitor section 5 v dc ex ref 1 gnd gnd ex ref 2 n/c gnd clock_out gnd pll tvl n/c hold over ref 1 ref 2 free run gnd n/c n/c tri-state n/c alarm out cntl a cntl b sync_out
preliminary data sheet #: tm021 p age 5 of 12 rev: p03 date: 06/27/01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice pin description table 5 pin # pin name pin information 1 hold over mode indicator. when the stm is in holdover mode, hold over will be a logic high output. 2 ref 1 mode indicator. when the stm is using external reference #1, ref 1 will be a logic high output. 3 ref 2 mode indicator. when the stm is using external reference #2, ref 2 will be a logic high output. 4 free run mode indicator. when the stm is in free run mode, free run will be a logic high output. 5 gnd ground. 6 n/c no connection required 7 n/c no connection required 8 tri-state tri-state control for all outputs. 1=hi-z, 0=normal. 9 n/c no connection required 10 alarm out alarm indicator output. 11 cntl a mode control input. 12 cntl b mode control input. 13 pll tvl tuning voltage alarm. 14 gnd ground. 15 sync_out system clock output. 16 n/c no connection required 17 gnd ground. 18 clock_out an independent stratum 3 clock output with the required 4.6 ppm. can be used for general purpose clocking needs. 19 n/c no connection required 20 gnd ground. 21 ex ref 2 external reference #2 input. 22 gnd ground. 23 ex ref 1 external reference #1 input. 24 +5 v dc +5 volt dc supply. (vcc)
preliminary data sheet #: tm021 p age 6 of 12 rev: p03 date: 06/27/01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice operational mode change timing diagram figure 5 loss of reference timing diagram figure 6 d t tvl limit high frequency tvl limit low frequency sync_out tvl alarm & alarm out 0 < t < 2.125 msec *the dac is updated only when the output chan g es level. the maximum update rate is 8 khz d (nominal frequency) voltage controlled ocxo voltage (v) frequenc y (ppm) 0.5 v 3.8 v ma x = 14ppm min 9ppm mi n = -9ppm max -14ppm 0.300 0.350 0.400 0.450 0.500 0.550 0.600 012345678 elapsed time (min) current (a) tvl alarm timing diagram figure 7 tvl alarm range figure 8 maximum current draw figure 9 mounting clearances figure 10 2 msec < t < 4.125 msec d m change in operational mode operational mode indicator d t m .030" pin land all solder and/or wire tags shall not extend more than .020" below pc board bottom surface .020" .020" max. external reference input alarm ton a toff a 2 msec < t on < 6.125 msec 0 msec < t off < 2.125 msec a a
preliminary data sheet #: tm021 p age 7 of 12 rev: p03 date: 06/27/01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice typical system test set-up figure 11 target system under test possible choices include stanford research model: fs700 truetime model xxx arbitrary waveform generator external reference input arbitrary waveform generator [noise source] ds1 rate rz (1.544 mhz), e1 rate rz or 8 khz clock rz with noise modulation tektronix sj300e clock or bits logic level clock input (ttl, cmos, etc.) hp53310a modulation analyzer / time interval analyzer ds1 rate [1.544 mhz] bits bipolar phase error data output s ample wan de r g en e ration (t d e v) for s t m /m s t m -s3 10 0.0e -1 2 1.0 e-9 10.0 e-9 1 00.0 e-9 1.0 e-6 10.0e-3 100 .0e -3 1 .0e +0 1 0.0 e+0 100 .0e +0 1.0 e+3 in te g r a tio n time (s e c ) tdev (se c tdev gr1244-fig5.1 gr1244-fig5-3 t ypical res pons e - 3 00 0 s eco nd tes t - j itter applied (2 ui @ 10 h z) ref date a p r 2 2 1998 kdh c o py ri ght 199 8 c o nno r -w i nf iel d al ll rights r es e rv ed s a mple m t ie d ata for s t m -s 3/m st m -s 3 1.0e-9 10 .0e -9 100.0e-9 1.0e-6 1 00 .0 e-3 1.0e +0 10 .0e +0 1 00 .0 e+0 1.0 e+3 1 0.0 e+3 observation time (s) mtie (s mtie 1244-5.2 mas k (a ) 1244-5.2 mas k (b) 1244-5.6 mask gr253-5.4.4.3.2 c opyright 1998 c onnor-winfield all rights res er ved t ypi c al r es p o n s e - 3 0 0 0 s e co n d t e s t - j it t e r a pp li ed ( 2 u i @ 1 0 h z ) ref date ap r 2 2 19 98 kdh standards compliance documents time-stamped ensemble based on absolute time reference (10mhz input) ds-1, oc-3, oc-12 electrical or optical signals wander analyzer data (ieee-488) 10 mhz this device supplies system time information. it can be thought of as supplying "absolute time" reference information 10 mhz external reference input noise modulation input 10 mhz external reference input ieee-488 controller platform for software hp 53305a phase analyzer hp e1748a sync measurement tektronix wander analyzer 10 mhz external reference input timing card line card timing card oc-3 line card oc-12 line card oc-48 line card ds-1 line card . . . . ... mtie, tdev, wander transfer, and wander generation plots tektronix sj300e gps or loran timing source
preliminary data sheet #: tm021 p age 8 of 12 rev: p03 date: 06/27/01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice typical mtie - over temperature with noise figure 12 typical tdev - over temperature with noise figure 13 yp 0.01 0.1 1 10 0.01 0.1 1 10 100 1000 10000 10000 0 observation time (sec) tdev (ns) tdev (ns ) gr-1244-core mask yp 1 10 100 0.01 0.1 1 10 100 1000 10000 100 0 observation interval (sec) mtie (ns) mtie (ns) gr-1244-core mask
preliminary data sheet #: tm021 p age 9 of 12 rev: p03 date: 06/27/01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice 1 s phase transient figure 14 reference switching phase transient figure 15 g 1 10 100 1000 10000 0.01 0.1 1 10 100 100 0 observation time (sec) mtie (ns) mtie (ns) gr-253-core mask observation time (sec) mtie (ns) mtie (ns) gr-253-core mask
preliminary data sheet #: tm021 p age 10 of 12 rev: p03 date: 06/27/01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice hold over entry and exit with same reference figure 1 wander transfer figure 17 1 10 100 1000 10000 0.01 0.1 1 10 10 0 observation interval mtie (ns) entry exit gr-253-core mask 0.1 1 10 100 1000 0.01 0.1 1 10 100 1000 1000 0 observation time (sec) tdev (ns) wander transfer gr-253-core mask
preliminary data sheet #: tm021 p age 11 of 12 rev: p03 date: 06/27/01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice notes: 1.0 stresses beyond those listed under absolute maximum rating may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under recommended operating conditions is not implied. exposure ot absolute maximum ratings conditions for extended periods of time may affect device reliability. 2.0 power-on reset will be acivated within this level. 3.0 nominal signal into a cmos load is usually 3v or greater. 4.0 hold over stability is the cumulative fractional frequency offset containing initial offset, temperature, and drift components as described by bellcore gr-1244-core 5.2. 5.0 pull-in range is the maximum frequency deviation on the reference inputs to the timing module that can be overcome to pull itself into synchronization with the reference. 6.0 after 100 seconds at stable room temperature. ordering information: stm-s3+ ? 16.384 mhz stm-s3+ ? 19.44 mhz stm-s3+ ? 38.88 mhz revision revision date note p00 6/29/00 preliminary informational release p01 2/05/00 changed format p02 2/27/01 minor corrections p03 6/27/01 reformatted layout
data sheet #: tm021 p age 12 of 12 rev: 0 2 date: 02/27/01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice

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